An A100 SM has ~164 KB of shared memory. A TPU v5e has ~128 MB of VMEM — roughly 800x more on-chip space. Bigger tiles fit on-chip, more data reuse per HBM load. Same tiling tradeoff from Part 4 — bigger tiles = more reuse but must fit in SRAM — just with a much higher ceiling on TPU.
Interpolation matrix in the Lagrange basis，这一点在heLLoword翻译中也有详细论述
。关于这个话题，手游提供了深入分析
Works with every ESP and CRM
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